An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Automatic generation of customized discrete fourier transform IPs
Proceedings of the 42nd annual Design Automation Conference
Multi-port interconnection networks for radix-R algorithms
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Analysis of twiddle factor memory complexity of radix-2ipipelined FFTs
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
"Smart" design space sampling to predict Pareto-optimal solutions
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
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This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator allows a user to make customized tradeoffs between cost and performance and between utilization of different resource classes. The equation-based resource model permits immediate and accurate estimation of resource requirements as the user considers the different generator options. Furthermore, the fast turnaround of the model allows it to be combined with a search algorithm such that the user could query automatically for an optimal design within the stated performance and resource constraints.Following a brief review of the DFT IP generator, this paper presents the development of the equation-based models for estimating slice and hard macro utilizations in the Xilinx Virtex-II Pro FPGA family. The evaluation section shows that an average error of 6.1% is achievable by a model of linear equations that can be evaluated in sub-microseconds. The paper further offers a demonstration of the automatic design exploration capability.