Circuits, Systems, and Signal Processing
Computational frameworks for the fast Fourier transform
Computational frameworks for the fast Fourier transform
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
SPL: a language and compiler for DSP algorithms
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms
IEEE Transactions on Parallel and Distributed Systems
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Fast and accurate resource estimation of automatically generated custom DFT IP cores
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
FFT program generation for shared memory: SMP and multicore
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Formal datapath representation and manipulation for implementing DSP transforms
Proceedings of the 45th annual Design Automation Conference
Permuting streaming data using RAMs
Journal of the ACM (JACM)
Algebraic signal processing theory: Cooley-Tukey type algorithms for real DFTs
IEEE Transactions on Signal Processing
Radix rkFFTs: matricial representation and SDC/SDF pipeline implementation
IEEE Transactions on Signal Processing
A rewriting system for the vectorization of signal transforms
VECPAR'06 Proceedings of the 7th international conference on High performance computing for computational science
Automatic generation of streaming datapaths for arbitrary fixed permutations
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture-oriented regular algorithms for discrete sine andcosine transforms
IEEE Transactions on Signal Processing
Constant geometry algorithm for discrete cosine transform
IEEE Transactions on Signal Processing
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Compiling Scilab to high performance embedded multicore systems
Microprocessors & Microsystems
Hi-index | 0.00 |
Linear signal transforms such as the discrete Fourier transform (DFT) are very widely used in digital signal processing and other domains. Due to high performance or efficiency requirements, these transforms are often implemented in hardware. This implementation is challenging due to the large number of algorithmic options (e.g., fast Fourier transform algorithms or FFTs), the variety of ways that a fixed algorithm can be mapped to a sequential datapath, and the design of the components of this datapath. The best choices depend heavily on the resource budget and the performance goals of the target application. Thus, it is difficult for a designer to determine which set of options will best meet a given set of requirements. In this article we introduce the Spiral hardware generation framework and system for linear transforms. The system takes a problem specification as input as well as directives that define characteristics of the desired datapath. Using a mathematical language to represent and explore transform algorithms and datapath characteristics, the system automatically generates an algorithm, maps it to a datapath, and outputs a synthesizable register transfer level Verilog description suitable for FPGA or ASIC implementation. The quality of the generated designs rivals the best available handwritten IP cores.