Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A hypergraph-based model for port allocation on multiple-register-file VLIW architectures
International Journal of Parallel Programming
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Framework for High Level Estimations of Signal Processing VLSI Implementations
Journal of VLSI Signal Processing Systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
The Garp Architecture and C Compiler
Computer
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Application-specific customization of parameterized FPGA soft-core processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Near-optimal instruction selection on dags
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Efficient hardware code generation for FPGAs
ACM Transactions on Architecture and Code Optimization (TACO)
Design flow for embedded FPGAs based on a flexible architecture template
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Image Coprocessor: A Real-Time Approach Towards Object Tracking
ICDIP '09 Proceedings of the International Conference on Digital Image Processing
A soft multi-core architecture for edge detection and data analysis of microarray images
Journal of Systems Architecture: the EUROMICRO Journal
Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance
SASP '10 Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors (SASP)
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable object detection accelerators on FPGAs using custom design space exploration
SASP '11 Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors
Improving performance of nested loops on reconfigurable array processors
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 49th Annual Design Automation Conference
A systematic approach to classify design-time global scheduling techniques
ACM Computing Surveys (CSUR)
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A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.