Dataflow-driven memory allocation for multi-dimensional signal processing systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling with register constraints for DSP architectures
Integration, the VLSI Journal
A new approach to the multiport memory allocation problem in data path synthesis
Integration, the VLSI Journal
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
CAD challenges in multimedia computing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Exact evaluation of memory size for multi-dimensional signal processing systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fast Algorithms for Digital Signal Processing
Fast Algorithms for Digital Signal Processing
Computer Architecture; A Quantitative Approach
Computer Architecture; A Quantitative Approach
Estimation and design algorithms for the behavioral synthesis of asics
Estimation and design algorithms for the behavioral synthesis of asics
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
ACM Transactions on Architecture and Code Optimization (TACO)
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This paper deals with the presentation of a framework for the rapid prototyping of Digital Signal Processing applications. The BSS framework enables both synthesis of dedicated VLSI circuits and cost, performance estimation. The latter can be used at different accuracy levels and can help the designer in selecting a proper algorithm in order to improve the global performance of its implementation. The cost estimation takes into account both the processing unit, including operators, registers, interconnections, and memory units. The implemented estimation techniques are presented and include functional unit number bound calculation, probabilistic cost estimation of processing unit components, and memory unit area evaluation. We demonstrate, on a real application, that cost/signal processing quality trade-offs can be achieved while changing the type of algorithm and the number of filter taps for a given algorithm specification.