Exact evaluation of memory size for multi-dimensional signal processing systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A transformation-based approach for storage optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Background memory management for dynamic data structure intensive processing systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Architectural exploration and optimization of local memory in embedded systems
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting off-chip memory access modes in high-level synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
High-level library mapping for memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Framework for High Level Estimations of Signal Processing VLSI Implementations
Journal of VLSI Signal Processing Systems
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 14th international symposium on Systems synthesis
Systematic data reuse exploration methodology for irregular access patterns
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Data reorganization engines for the next generation of system-on-a-chip FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 42nd annual Design Automation Conference
Power aware data type refinement for the HIPERLAN/2
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing systems. In this paper, a novel background memory allocation and assignment technique is presented. It is intended for a behavioural algorithm specification, where the procedural ordering of the memory related operations is not yet fully fixed. Instead of the more restricted classical scheduling-based explorations, starting from procedurally interpreted specifications in terms of loops, a novel optimization approach—driven by data flow analysis—is proposed. Employing the estimated silicon area as a steering cost, this allocation/assignment technique yields one or (optionally) several distributed (multi-port) memory architecture(s) with fully-determined characteristics, complying with a given clock cycle budget for read/write operations. Moreover, our approach can accurately deal with complex multi-dimensional signals by means of a polyhedral data-flow analysis operating with groups of scalars.