Dataflow-driven memory allocation for multi-dimensional signal processing systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Array mapping in behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An integrated algorithm for memory allocation and assignment in high-level synthesis
Proceedings of the 39th annual Design Automation Conference
Locality-conscious process scheduling in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the 40th annual Design Automation Conference
Incorporating DRAM access modes into high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HyMacs: hybrid memory access optimization based on custom-instruction scheduling
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Cycle count accurate memory modeling in system level design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It has been known that there are high variations in memory access delays depending on the ways of designing memory configurations and assigning arrays to memories. Furthermore, embedded DRAM technology that provides efficient access modes is actively developed, possibly becoming a mainstream in future embedded system design. In that context, in this paper we propose an effective solution to the problem of (embedded DRAM) memory allocation and mapping in memory access code generation with the objective of minimizing the total memory access time. Specifically, the proposed approach, called MACCESS-opt, solves the three problems simultaneously: (i) determination of memories, (ii) mapping of arrays to memories, and (iii) scheduling of memory access operations, so that the use of DRAM access modes is maximized while satisfying the storage size constraint of embedded system. Experimental data on a set of benchmark designs are provided to show the effectiveness of the proposed integrated approach. In short, MACCESS-opt reduces the total memory access latency by over 18%, from which we found that our memory mapping and scheduling techniques in MACCESS-opt contribute about 12% and 6% reductions of total memory access latency, respectively.