Simulated annealing: theory and applications
Simulated annealing: theory and applications
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Array-data flow analysis and its use in array privatization
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Definition and solution of the memory packing problem for field-programmable systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Hidden Markov modeling and fuzzy controllers in FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level library mapping for memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Array allocation taking into account SDRAM characteristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Proceedings of the 42nd annual Design Automation Conference
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
International Journal of Reconfigurable Computing - Selected Papers from SPL 2008: Programmable Logic and Applications
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
ACM Transactions on Embedded Computing Systems (TECS)
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Abstract: This paper discusses the mapping of arrays in a behavior to memories in an implementation. We introduce a design representation based on a variety of array grouping techniques and the binding of array groups to memory components with different dimensions, access times, and number of ports. The results of design actions are computed in terms of the number of memory components and the length of schedules in the behavior. We demonstrate the ability of a synthesis tool using this representation to generate designs that span the entire range of the memory design space.