Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ISIS: a system for performance driven resource sharing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
The attributed-behavior abstraction and synthesis tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
Array mapping in behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Register estimation in unscheduled dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Applications of attributed-behavior synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A general consistency technique for increasing the controllability of high level synthesis tools
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficiency improvements for force-directed scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Achieving Design Closure Through Delay Relaxation Parameter
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of VLSI Signal Processing Systems
Storage assignment during high-level synthesis for configurable architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified approach for scheduling and allocation
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a single high level synthesis algorithm that schedules the operations of a data dependence graph, allocates the necessary hardware, and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph.