Optimum and heuristic data path scheduling under resource constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Scheduling under resource constraints and module assignment
Integration, the VLSI Journal
An effective methodology for functional pipelining
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Superpipelined control and data path synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Heuristics for branch-and-bound global allocation
EURO-DAC '92 Proceedings of the conference on European design automation
GSA: scheduling and allocation using genetic algorithm
EURO-DAC '94 Proceedings of the conference on European design automation
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Register estimation in unscheduled dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Component selection in resource shared and pipelined DSP applications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High-Level Synthesis of Recoverable Microarchitectures
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Cone Based Clustering for List Scheduling Algorithms
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A method for area estimation of data-path in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating bottom-up design into hardware synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Synthesis of Data Paths in Digital Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A transformation-based method for loop folding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Datapath synthesis using a problem-space genetic algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved force-directed scheduling in high-throughput digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a methodology for the integration of scheduling and allocation in high-level synthesis. It shows how a previous global analysis of the data flow graph structure and the module library features can be used as an appropriate guide to accelerate the process of finding solutions in the design space. Several bounding and guiding heuristics for a branch-and-bound-based exploration are presented. In addition to dealing with basic blocks, the scheduling and allocation method addresses also the treatment of conditional branches and loops.