Cone Based Clustering for List Scheduling Algorithms

Authors:
Sriram Govindarajan;Ranga Vemuri
Affiliations:
Laboratory for Digital Design Environments, Department of ECECS, P.O. Box 210030, University of Cincinnati, Cincinnati, OH;Laboratory for Digital Design Environments, Department of ECECS, P.O. Box 210030, University of Cincinnati, Cincinnati, OH
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 6
Cited 9

Introduction to artificial neural systems

Introduction to artificial neural systems
Practical Digital Video with Programming Examples in C

Practical Digital Video with Programming Examples in C
Digital Filters and Signal Processing

Digital Filters and Signal Processing
High Performance Compilers for Parallel Computing

High Performance Compilers for Parallel Computing
High-Level Synthesis for Real-Time Digital Signal Processing

High-Level Synthesis for Real-Time Digital Signal Processing
High-Level VLSI Synthesis

High-Level VLSI Synthesis

Improving the schedule quality of static-list time-constrained scheduling (poster paper)

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs

Formal Methods in System Design - Special issue on formal methods for computer-added design
Integrated high-level synthesis and power-net routing for digital design under switching noise constraints

Proceedings of the 38th annual Design Automation Conference
Module Allocation for Dynamically Reconfigurable Systems

IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A cycle-accurate compilation algorithm for custom pipelined datapaths

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A unified approach for scheduling and allocation

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

List scheduling algorithms attempt to minimize latency under resource constraints using a priority list. We propose a new heuristic that can be used in conjunction with any priority function. At each time-step, the proposed clustering heuristic tries to find a best match between ready operations and the resource set. The heuristic arbitrates among equal priority operations based on operation-clusters formed from the dependency graph. Based on this heuristic we have presented a new Cone-Based List Scheduling (\CBLS\@) algorithm. Results presented in this paper compare \CBLS\ with the well-known Force Directed List Scheduling (\FDLS\@) algorithm, for several synthesis benchmarks. In cases where \FDLS\ produces sub-optimal schedules, \CBLS\ produces better schedules and in other cases \CBLS\ performs as good as \FDLS\@. Moreover, in conjunction with a simple priority function (namely the self-force of an operator), \CBLS\ results in considerable improvement in latency when compared to \FDLS\ that has the same priority function. Finally, we show that \CBLS\ with the simple priority function performs better in execution time as well as latency when compared to the original \FDLS\ that has a relatively complex priority function.