Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Cone Based Clustering for List Scheduling Algorithms
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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The synthesis of dynamically reconfigurable systems poses some new challenges for high-level synthesis tools. In this paper, we deal with the task of module allocation as this step has a direct influence on the performance of the dynamically reconfigudreasbiglne. We propose a configuration bundling driven module allocation technique that can be used for component clustering. The basic idea is to group configurable logic together properly so that a given configuration can do as much work as possible, allowing a greater portion of the task to be completed between reconfigurations. Our synthesis methodology addresses the issues of minimizing reconfiguration overhead by maintaining a global view of the resource requirements at all times during the high-level synthesis process.