Control optimization based on resynchronization of operations
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An integer programming approach to instruction implementation method selection problem
EURO-DAC '92 Proceedings of the conference on European design automation
High-level synthesis in a rapid-prototype environment for mechatronic systems
EURO-DAC '92 Proceedings of the conference on European design automation
Semantics and synthesis of signals in behavioral VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Structured design methodology for high-level design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hardware-software-codesign of application specific microcontrollers with the ASM environment
EURO-DAC '94 Proceedings of the conference on European design automation
100-hour design cycle: a test case
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Semi-dynamic scheduling of synchronization-mechanisms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Clock-driven performance optimization in interactive behavioral synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
An efficient representation for formal synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units
Journal of VLSI Signal Processing Systems
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Forward-looking objective functions: concept & applications in high level synthesis
Proceedings of the 39th annual Design Automation Conference
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Formal Methods in System Design
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
Introduction to High-Level Synthesis
IEEE Design & Test
ADPCM codec: from system level description to versatile HDL model
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Cone Based Clustering for List Scheduling Algorithms
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Transformations for functional verification of synthesized designs
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design flow for hardware/software cosynthesis of a video compression system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A VLSI DESIGN DESIGN-SYNTHESIS METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL
Journal of Integrated Design & Process Science
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design of a pipelined datapath synthesis system for digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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