A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-Level VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Controller Testability Analysis and Enhancement Technique
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Integrated High-Level Test Synthesis for Built-in Self-Testable Designs
Proceedings of the 14th symposium on Integrated circuits and systems design
Built-In Self-Testable Date Path Synthesis
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Optimization of bist resources during high-level synthesis
Optimization of bist resources during high-level synthesis
Circular BIST with partial scan
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Testing of a fabricated chip is a process that applies a sequence of inputs to the chip and analyzes the chip's output sequence to ascertain whether it functions correctly. As the chip density grows to beyond millions of gates, Embedded systems and systems-on-chip testing becomes a formidable task. Vast amounts of time and money have been invested by the industry just to ensure the high testability of products. On the other hand, as design complexity drastically increases, current gate-level design and test methodology alone can no longer satisfy stringent time-to-market requirements. The High-Level Test Synthesis (HLTS) system, which this paper mainly focuses on, is to develop new systematic techniques to integrate testability consideration, specially the Built-In Self-Test (BIST) methodology, into the synthesis process. It makes possible for an automatic synthesis tool to predict testability of the synthesized embedded systems or chips accurately in the early stage. It also optimizes the designs in terms of test cost as well as performance and hardware area cost.