Introduction to information theory
Introduction to information theory
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Statistical Theory of Digital Circuit Testability
IEEE Transactions on Computers
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A Testability Strategy for Microprocessor Architecture
IEEE Design & Test
Implementing Macro Test in Silicon Compiler Design
IEEE Design & Test
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
On testable multipliers for fixed-width data path architectures
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Design of Testable Multipliers for Fixed-Width Data Paths
IEEE Transactions on Computers
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A test synthesis technique using redundant register transfers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems
Journal of Electronic Testing: Theory and Applications
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Testability Enhancement for Control-Flow Intensive Behaviors
Journal of Electronic Testing: Theory and Applications
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Partial BIST insertion to eliminate data correlation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A method for testability analysis and BIST insertion at the RTL
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Efficient Implementation of Multiple On-Chip Signature Checking
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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