Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Design of a C-testable booth multiplier using a realistic fault model
Journal of Electronic Testing: Theory and Applications
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Concrete Math
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability Using Architectural Descriptions
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
High-level synthesis of digital circuits using global scheduling and binding algorithms
High-level synthesis of digital circuits using global scheduling and binding algorithms
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fixed-Width Multiplier for DSP Application
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.