INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Test register insertion with minimum hardware cost
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Design of Testable Multipliers for Fixed-Width Data Paths
IEEE Transactions on Computers
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Synthesis of Native Mode Self-Test Programs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
BISTing Datapaths under Heterogeneous Test Schemes
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
On ILP formulations for built-in self-testable data path synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A STAFAN-like functional testability measure for register-level circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
Synthesis of Testable Pipelined Datapaths Using Genetic Search
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Graph-Theoretic Approach for Register File Based Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
A wiring-aware approach to minimizing built-in self-test overhead
Journal of Computer Science and Technology
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-Testing: Granting Testability in a Codesign Environment
Integrated Computer-Aided Engineering
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 0.01 |