High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Journal of Electronic Testing: Theory and Applications
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Generating Reliable Embedded Processors
IEEE Micro
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Methodology for Designing Optimal Self-Checking Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Error Detection in Fault Secure Controllers using State Encoding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
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Self test strategies for processors in embedded core-basedsystems have recently found great attention fortwo reasons. First, production test for embedded coresis becoming a problem due to inaccessible processorpins. Second, self test is a very desirable feature forprocessors in applications that require a high level ofdependability over a long life time. Standard processorsor processor-cores used in embedded systems are notaccessible for a full-scale redesign. Therefore methodsmust be developed that facilitate self-test by keeping theoriginal cores as unharmed as possible. The approachpresented here duplicates only the truly necessary partsof a standard processors for test and back-up purposesincluding capabilities of on-line self test. Transientfaults are recognized and compensated. In a secondstep, the back-up processor itself becomes fully self-testingand fault tolerant towards a highly dependablesystem solution by state-encoding of control paths andBerger code check in the data path.