NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
A unified approach to the decomposition and re-decomposition of sequential machines
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
FSM decomposition revisited: Algebraic structure theory applied to MCNC benchmark FSMs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
MIS: A Multiple-Level Logic Optimization System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Detecting undetectable controller faults using power analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesizing Fast, Online-Testable Control Units
IEEE Design & Test
Generating Reliable Embedded Processors
IEEE Micro
Fast Controllers for Data Dominated Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
14.1 Fast Self-Recovering Controllers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
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The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms.