An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault-tolerant computer system design
Fault-tolerant computer system design
Electromigration: the time bomb in deep-submicron ICs
IEEE Spectrum
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Introducing Core-Based System Design
IEEE Design & Test
Fault Tolerant VLSI Design with Functional Block Redundancy
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A method to derive application-specific embedded processing cores
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Application of design patterns for hardware design
Proceedings of the 40th annual Design Automation Conference
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automatic architecture refinement techniques for customizing processing elements
Proceedings of the 45th annual Design Automation Conference
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
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A new approach to enhance the reliability of embedded processor-based systems is presented. It was developed for applications with high-reliability demands under heavy cost-constraints. The concept is a minimized duplication of processor macro-components in programmable logic devices in accordance with the application of the embedded system. This concept is described in detail with the design flow of the processor control structure as an example. We show that the hardware overhead and the costs of classical fault-tolerant techniques like triple-modular redundant (TMR) component implementation can be reduced significantly. Furthermore, we show the possibilities and limitations of programmable logic devices used in this approach.