Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors
Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing
Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction
IEEE Transactions on Computers
Customized instruction-sets for embedded processors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Data Dependence Analysis of Assembly Code
International Journal of Parallel Programming - Special issue on instruction-level parallelism and parallelizing compilation, part 2
Generating Reliable Embedded Processors
IEEE Micro
A New Facility for Dynamic Control of Program Execution: DELI
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
DELI: a new run-time control point
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
LLVA: A Low-level Virtual Instruction Set Architecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 4.10 |
A quantum leap in a compiler's ability to automatically extract parallelism from code would have enormous ramifications for future architectures, although the issue of compatibility with legacy software also hinders architectural innovation. The author describes walk-time techniques-translation techniques that change code after it is distributed. He contends that these techniques will lead to families of very different, yet surprisingly compatible, CPUs that are customized to specific application areas.