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Communications of the ACM - Special issue on digital multimedia systems
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Performance of a software MPEG video decoder
MULTIMEDIA '93 Proceedings of the first ACM international conference on Multimedia
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Realtime MPEG video via software decompression on a PA-RISC processor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Switcherland: a QoS communication architecture for workstation clusters
Proceedings of the 25th annual international symposium on Computer architecture
Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Simple vector microprocessors for multimedia applications
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Evaluating MMX technology using DSP and multimedia applications
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
A bitmap scaling and rotation design for SH1 low power CPU
MSWiM '99 Proceedings of the 2nd ACM international workshop on Modeling, analysis and simulation of wireless and mobile systems
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits
Journal of VLSI Signal Processing Systems
Reconfigurable media processing
Parallel Computing - Parallel computing in image and video processing
Transitioning Desktops to Set Tops
IEEE Design & Test
IEEE Micro
Subword Parallelism with MAX-2
IEEE Micro
SH-5: The 64-Bit SuperH Architecture
IEEE Micro
Compiling for SIMD Within a Register
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Multimedia Extensions and Sub-word Parallelism in Image Processing: Preliminary Results
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Exploiting data-width locality to increase superscalar execution bandwidth
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Design and characterization of the Berkeley multimedia workload
Multimedia Systems
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
General-Purpose Processor Huffman Encoding Extension
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An extended ANSI C for processors with a multimedia extension
International Journal of Parallel Programming
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing
Journal of VLSI Signal Processing Systems
Software optimization of video codecs on pentium processor with MMX technology
EURASIP Journal on Applied Signal Processing
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
MediaBench II video: Expediting the next generation of video systems research
Microprocessors & Microsystems
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SHA: a design for parallel architectures?
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
Data dependence analysis for intra-register vectorization
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
On dependence analysis for SIMD enhanced processors
VECPAR'04 Proceedings of the 6th international conference on High Performance Computing for Computational Science
A programming model for an embedded media processing architecture
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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This article defines multimedia, and motivates the use of multimedia benchmarks in the design of general-purpose computers and general-purpose microprocessors. It describes a minimalistic set of multimedia instructions introduced into PA-RISC microprocessors that allow sophisticated SIMD-MIMD parallelism to be implemented, with insignificant changes to the underlying microprocessor. This enabled for the first time, a video decoder implemented in software to attain MPEG video and audio decompression and playback at realtime rates of 30 frames per second, on an entry-level workstation.Unlike previous approaches, no special DSP, coprocessor or functional unit was added to the microprocessor. The multimedia instructions include parallel subword add, subtract, average, shift_left_and_add andshift_right_and_add instructions. Signed, and a novel form of unsigned saturation, is also supported. These general-purpose parallel subword instructions are useful for accelerating a variety of multimedia programs.