Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits

  • Authors:
  • Vasily G. Moshnyaga

  • Affiliations:
  • Department of Electronics Engineering and Computer Science, Fukuoka University, 8-19-1 Nanakuma, Jonan-ku, Fukuoka 814-0180, Japan

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2002

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Abstract

Reducing switching activity of Arithmetic and Logic Unit (ALU) is important for design of low-power processors. Due to two's complement data notation and fixed bit-width, existing ALUs perform many redundant signal transitions during subtraction, dissipating power. This paper proposes a new scheme that adaptively adjusts the ALU bit-width to input data variation. Unlike related techniques, the scheme masks the number of the Most Significant Bits whose values remain unchanged, thus preserving unnecessary signal variations in corresponding hardware. The scheme is simple in implementation yet efficient in performance. According to simulations, it can reduce the total number of signal transitions per subtraction as much as half and save up to 30% of energy/operation without sacrificing the quality of results.