Energy reduction by systematic run-time reconfigurable hardware deactivation

Authors:
W. G. Osborne;W. Luk;J. G. F. Coutinho;O. Mencer
Affiliations:
Department of Computing, Imperial College London, UK;Department of Computing, Imperial College London, UK;Department of Computing, Imperial College London, UK;Department of Computing, Imperial College London, UK
Venue:
Transactions on High-Performance Embedded Architectures and Compilers IV
Year:
2011

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Abstract

This paper describes a method of developing energy-efficient run-time reconfigurable hardware designs. The key idea is to systematically deactivate part of the hardware using word-length optimisation techniques, and then select the most optimal reconfiguration strategy: multiple bitstream reconfiguration or component multiplexing. When multiplexing between different parts of the circuit, it may not always be possible to gate the clock to the unwanted components in FPGAs. Different methods of achieving the same effect while minimising the area used for the control logic are investigated. A model is used to determine the conditions under which reconfiguring the bitstream is more energy-efficient than multiplexing part of the design, based on power measurements taken on 130nm and 90nm devices. Various case studies, such as ray tracing, B–Splines, vector multiplication and inner product are used to illustrate this approach.