Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Microprocessors & Microsystems
Reconfigurable hardware for high-security/high-performance embedded systems: the SAFES perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Power characterisation for fine-grain reconfigurable fabrics
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Energy reduction by systematic run-time reconfigurable hardware deactivation
Transactions on High-Performance Embedded Architectures and Compilers IV
A signature-based power model for MPSoC on FPGA
VLSI Design
UPaRC: ultra-fast power-aware reconfiguration controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The power consumption of reconfigurable systems has become a fundamental aspect in designing applications. Especially for mobile systems with a limited power supply, it is necessary to identify and optimize the power loss. Moreover, it is essential to evaluate duringapplication development time exact power trade-offs, especially including the consideration of the dynamic reconfiguration phases of corresponding devices, e.g. Virtex-Series from Xilinx. This paper discusses the exact power consumption trade-offs between the measured runtimeconsumption of a mapped application and the measured reconfiguration-time consumption of different dynamically (partially and completely) reconfigured applications. Moreover, the possibilities and limitations of today麓s available power estimation tools are discussed and compared to the exact measurements.