Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Genetic algorithms + data structures = evolution programs (3rd ed.)
Genetic algorithms + data structures = evolution programs (3rd ed.)
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Embedded System Design: A Unified Hardware/Software Introduction
Embedded System Design: A Unified Hardware/Software Introduction
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating an IR Automatic Target Recognition Application with FPGAs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method uses a new technique to compile Java programs directly to special-purpose processors that are called ''flowpaths''. Flowpaths allow a software program to be executed in such a way that one low-capacity FPGA is executing a piece of the program while a second low-capacity FPGA is being dynamically reconfigured to take over execution after the first one has completed its task. In this fashion, the program is executed by continuously alternating between the two chips. This process allows large programs to be implemented on limited hardware resources and at higher clock frequencies on an FPGA. The sequencer and rules for partitioning a flowpath are presented and the method is illustrated using a genetic algorithm compiled from Java directly to flowpaths using a flowpath compiler designed in our lab. The genetic algorithm flowpath requires 68% of an expensive, high-density Virtex2 XC2V8000 with a maximum frequency of 68.9MHz (this genetic algorithm would have required 285% of the smaller, more reasonably priced Virtex 1000). However, by splitting flowpaths as presented in this paper, the algorithm can be implemented with an average maximum clock frequency of 154.8MHz using only two low-capacity, inexpensive Virtex XCV50 chips, the smallest capacity of the Virtex family. The split flowpaths require one-quarter of the clock cycles used by the JStamp microcontroller. Therefore, instead of using an expensive high-density FPGA, the proposed design illustrates how a genetic algorithm can be implemented using only a pair of inexpensive chips that have only 50,000 equivalent gates each; a low-cost sequencer; and 11.81 MB of memory to store bit files. The overall time performance depends on the speed of the FPGA reconfiguration process.