The Challenges of Hardware Synthesis from C-Like Languages

  • Authors:
  • Stephen A. Edwards

  • Affiliations:
  • Columbia University, New York

  • Venue:
  • Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
  • Year:
  • 2005

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Abstract

MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: concurrency and timing control.