Multi-level logic simplification using don't cares and filters
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Introduction to algorithms
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Hardware synthesis from C/C++ models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
The design and implementation of an intentional naming system
Proceedings of the seventeenth ACM symposium on Operating systems principles
Automating first-order relational logic
SIGSOFT '00/FSE-8 Proceedings of the 8th ACM SIGSOFT international symposium on Foundations of software engineering: twenty-first century applications
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
The Designer's Guide to VHDL
Essential COM
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formula-Dependent Equivalence for Compositional CTL Model Checking
Formal Methods in System Design
Border-Block Triangular Form and Conjunction Schedule in Image Computation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Declarative symbolic pure-logic model checking
Declarative symbolic pure-logic model checking
Scalable compositional minimization via static analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
Sequential synthesis using S1S
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
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The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for modeling designs. The Alloy Analyzer translates Alloy formulas for a given scope, i.e., a bound on the universe of discourse, to Boolean formulas in conjunctive normal form (CNF), which are subsequently checked using propositional satisfiability solvers. We present SERA, a novel algorithm that compiles a relational logic formula for a given scope to a sequential circuit. There are two key advantages of sequential circuits: they form a more succinct representation than CNF formulas, sometimes by several orders ofmagnitude. Also sequential circuits are amenable to a range of powerful automatic analysis techniques that have no counterparts for CNF formulas. Our experiments show that SERA, used in conjunction with a sequential circuit analyzer, can check formulas for scopes that are an order of magnitude higher than those feasible with the Alloy Analyzer.