Verification of Real-Time Systems using Linear Relation Analysis
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Model checking
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
STeP: The Stanford Temporal Prover
STeP: The Stanford Temporal Prover
Approximate symbolic model checking using overlapping projections
Approximate symbolic model checking using overlapping projections
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Satisfiability Checking Using Boolean Expression Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Exploiting state encoding for invariant generation in induction-based property checking
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Principles of Sequential-Equivalence Verification
IEEE Design & Test
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
HW/SW co-verification of embedded systems using bounded model checking
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast illegal state identification for improving SAT-based induction
Proceedings of the 43rd annual Design Automation Conference
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Sequential Circuits for Relational Analysis
ICSE '07 Proceedings of the 29th international conference on Software Engineering
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Proceedings of the conference on Design, automation and test in Europe
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Using SAT-based techniques in power estimation
Microelectronics Journal
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Completeness in SMT-based BMC for software programs
Proceedings of the conference on Design, automation and test in Europe
Model checking with Boolean Satisfiability
Journal of Algorithms
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Scaling up the formal verification of Lustre programs with SMT-based techniques
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Discrete Event Dynamic Systems
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Safety Property Verification of Cyclic Synchronous Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
Using Satisfiability Modulo Theories for Inductive Verification of Lustre Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Experimental analysis of different techniques for bounded model checking
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A SAT characterization of boolean-program correctness
SPIN'03 Proceedings of the 10th international conference on Model checking software
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Software verification using k-induction
SAS'11 Proceedings of the 18th international conference on Static analysis
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Emulation of biological networks in reconfigurable hardware
Proceedings of the 2nd ACM Conference on Bioinformatics, Computational Biology and Biomedicine
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Binary Decision Diagrams (BDDs) have dominated the area of symbolic model checking for the past decade. Recently, the use of satisfiability (SAT) solvers has emerged as an interesting complement to BDDs. SAT-based methods are capable of coping with some of the systems that BDDs are unable to handle.The most challenging problem that has to be solved in order to adapt standard symbolic model checking to SAT-solvers is the boolean quanti fication necessary for traversing the state space. A possible approach to extending the applicability of SAT-based model checkers is therefore to reduce the amount of traversal.In this paper, we investigate a BDD-based verification algorithm due to van Eijk. Van Eijk's algorithm tries to compute information that is sufficient to prove a given safety property directly. When this is not possible, the computed information can be used to reduce the amount of traversal needed by standard model checking algorithms. We convert van Eijk's algorithm to use a SAT-solver instead of BDDs. We also make a number of improvements to the original algorithm, such as combining it with recently developed variants of induction. The result is a collection of substantially strengthened and complete verification methods that do not require state space traversal.