Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a gate-level representation of the circuit that facilitates the computation of effective invariants for induction-based property checking. Our experiments show the strong impact of state encoding on the efficiency of the induction process.