Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Incremental re-encoding for symbolic traversal of product machines
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
An ATPG-Based Framework for Verifying Sequential Equivalence
Proceedings of the IEEE International Test Conference on Test and Design Validity
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On Verifying the Correctness of Retimed Circuits
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimizing sequential verification by retiming transformations
Proceedings of the 37th Annual Design Automation Conference
Formal Methods in System Design
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Placement driven retiming with a coupled edge timing model
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
Exploiting state encoding for invariant generation in induction-based property checking
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using RTL Statespace Information and State Encoding for Induction Based Property Checking
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
On Extending Bounded Proofs to Inductive Proofs
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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This paper proposes a technique for sequential logic equivalence checking by a structural fixed point iteration. Verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techniques. These exploit structural similarity between designs by local circuit transformations. Starting from the initial state, for each time frame the performed circuit transformations are stored (recorded) in an instruction queue. In subsequent time frames the instruction queue is re-used (played) and updated when necessary. At some point the instruction queue does not need to be modified any more and is valid in all subsequent time frames. Thus, a fixed point is reached and machine equivalence is proved by induction. Experimental results show the great promise of this approach to verify circuits after resynthesis and retiming.