Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
A constructive approach towards correctness of synthesis-application within retiming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are re-positioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed. Here, we present a novel approach to check the correctness of a retimed circuit according to the definition of 3-valued equivalence. This approach is based on our verification framework using sequential ATPG techniques. We further incorporate an algorithm to pre- process the circuits and make the verification process even more efficient. We will present the experimental results of verifying the retimed circuits with hundreds of flip-flops on ISCAS89 benchmark circuits to show its capability.