AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Simplifying Circuits for Formal Verification Using Parametric Representation
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
On Verifying the Correctness of Retimed Circuits
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Efficient equivalence checking with partitions and hierarchical cut-points
Proceedings of the 41st annual Design Automation Conference
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable compositional minimization via static analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
Combinational techniques for sequential equivalence checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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We present several improvements to general-purpose sequential redundancy removal. (1) We propose using a robust variety of synergistic transformation and verification algorithms to process the individual proof obligations. This enables greater speed and scalability, and identifies a significantly greater degree of redundancy, than prior approaches. (2) We generalize upon traditional redundancy removal and utilize the speculatively-reduced model to enhance bounded search, without needing to complete any proofs.