Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Verification Using Uninterpreted Functions and Finite Instantiations
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential Circuits for Relational Analysis
ICSE '07 Proceedings of the 29th international conference on Software Engineering
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Information and Software Technology
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State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However, the complexity of computing the set of equivalent state pairs often exceeds that of performing symbolic property checking on the original system. We introduce a fully-automated efficient compositional minimization approach which requires only static analysis. Key to our approach is a heuristic algorithm that identifies components with high reduction potential in a bit-level netlist. We next inject combinational logic which restricts the component's inputs to selected representatives of symbolically-computed equivalence classes thereof. Finally, we use existing transformations to synergistically exploit the dramatic netlist reductions enabled by these input filters. Experiments confirm that our technique is able to efficiently yield substantial reductions on large industrial netlists.