Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Simplifying Circuits for Formal Verification Using Parametric Representation
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Bisimulation and Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable compositional minimization via static analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Proceedings of the conference on Design, automation and test in Europe
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
GLA: gate-level abstraction revisited
Proceedings of the Conference on Design, Automation and Test in Europe
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Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present several fully-automated techniques to enable maximal input reductions of sequential netlists. First, we present a novel min-cut based localization refinement scheme for yielding a safely overapproximated netlist with minimal input count. Second, we present a novel form of reparameterization: as a trace-equivalence preserving structural abstraction, which provably renders a netlist with input count at most a constant factor of register count. In contrast to prior research in reparameterization to offset input growth during symbolic simulation, we are the first to explore this technique as a structural transformation for sequential netlists, enabling its benefits to general verification flows. In particular, we detail the synergy between these input-reducing abstractions, and with other transformations such as retiming which – as with traditional localization approaches – risks substantially increasing input count as a byproduct of its register reductions. Experiments confirm that the complementary reduction strategy enabled by our techniques is necessary for iteratively reducing large problems while keeping both proof-fatal design size metrics – register count and input count – within reasonable limits, ultimately enabling an efficient automated solution.