Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Logic optimization using rule-based randomized search
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On resolution proofs for combinational equivalence
Proceedings of the 44th annual Design Automation Conference
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Algorithms for maximum satisfiability using unsatisfiable cores
Proceedings of the conference on Design, automation and test in Europe
Justification-Based Local Search with Adaptive Noise Strategies
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Justification-Based Non-Clausal Local Search for SAT
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
On the power of top-down branching heuristics
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 1
Simulation and SAT-based Boolean matching for large Boolean networks
Proceedings of the 46th Annual Design Automation Conference
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
C32SAT: checking C expressions
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Journal of Electronic Testing: Theory and Applications
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Nenofex: expanding NNF for QBF solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Node addition and removal in the presence of don't cares
Proceedings of the 47th Design Automation Conference
Integrated logic synthesis using simulated annealing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Dynamic data folding with parameterizable FPGA configurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DPLL+ROBDD Derivation applied to inversion of some cryptographic functions
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A constraint satisfaction approach for programmable logic detailed placement
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
Partial synthesis through sampling with and without specification
Proceedings of the International Conference on Computer-Aided Design
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Many tasks in computer-aided design (CAD), such as equivalence checking, property checking, logic synthesis, and false paths analysis, require efficient Boolean reasoning for problems derived from circuits. Traditionally, canonical representations, e.g., binary decision diagrams (BDDs), or structural satisfiability (SAT) methods, are used to solve different problem instances. Each of these techniques offer specific strengths that make them efficient for particular problem structures. However, neither structural techniques based on SAT, nor functional methods using BDDs offer an overall robust reasoning mechanism that works reliably for a broad set of applications. The authors present a combination of techniques for Boolean reasoning based on BDDs, structural transformations, an SAT procedure, and random simulation natively working on a shared graph representation of the problem. The described intertwined integration of the four techniques results in a powerful summation of their orthogonal strengths. The presented reasoning technique was mainly developed for formal equivalence checking and property verification but can equally be used in other CAD applications. The authors' experiments demonstrate the effectiveness of the approach for a broad set of applications.