Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
Formal Verification of the Pentium® 4 Floating-Point Multiplier
Proceedings of the conference on Design, automation and test in Europe
Defining the IEEE-854 Floating-Point Standard in PVS
Defining the IEEE-854 Floating-Point Standard in PVS
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of the cell broadband engine™ processor
Proceedings of the 43rd annual Design Automation Conference
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Functional verification of the IBM system z10 processor chipset
IBM Journal of Research and Development
Formal analysis of end-around-carry adder in floating-point unit
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Automatic verification of estimate functions with polynomials of bounded functions
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems
IBM Journal of Research and Development
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor's architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD- and SAT-based symbolic simulation. To make this verification task tractable, we use a combination of case-splitting, multiplier isolation, and automatic model reduction techniques. The case-splitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. Themethodology is directly applicable to multi-GHz industrial implementation models (e.g., HDL or gate-level circuit representations) that contain all details of the high-performancetransistor-level model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach.