Formal Methods in System Design
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Functional verification of the IBM system z10 processor chipset
IBM Journal of Research and Development
IBM POWER7 multicore server processor
IBM Journal of Research and Development
Adaptive energy-management features of the IBM POWER 7 chip
IBM Journal of Research and Development
IBM Journal of Research and Development
Hi-index | 0.00 |
This paper describes the methods and techniques used to verify the POWER7® microprocessor and systems. A simple linear extension of the methodology used for POWER4®, POWER5®, and POWER6® was not possible given the aggressive design point and schedule of the POWER7 project. In addition to the sheer complexity of verifying an eight-core processor chip with scalability to 32 sockets, central challenges came from the four-way simultaneous multithreading processor core, a modular implementation structure with heavy use of asynchronous interfaces, aggressive memory subsystem design with numerous new reliability, availability, and serviceability (RAS) advances, and new power management and RAS mechanisms across the chip and the system. Key aspects of the successful verification project include a systematic application of IBM's random-constrained unit verification, unprecedented use of formal verification, thread-scaling support in core verification, and a consistent use of functional coverage across all verification disciplines. Functional coverage instrumentation, which is combined with the use of the newest IBM hardware simulation accelerator platform, enabled coverage-driven development of postsilicon exercisers in preparation of bring-up, a foundation for the desired systematic linkage of presilicon and postsilicon verification. RAS and power management verification also required new approaches, extending these disciplines to span all the way from the unit level to the end-to-end scenarios using the hardware accelerators.