Functional formal verification on designs of pSeries microprocessors and communication subsystems

  • Authors:

  • R. M. Gott;J. R. Baumgartner;P. Roessler;S. I. Joe

  • Affiliations:

  • -;-;-;-

  • Venue:
  • IBM Journal of Research and Development - POWER5 and packaging
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper discusses our experiences and results in applying functional formal verification (FFV) techniques to the design of the IBM pSeries® microprocessor and communication subsystem. We describe the evolution of FFV deployment across several generations of this product line, including tool and algorithmic improvements, as well as methodological improvements for prioritizing the portions of the design that should be considered for formal verification coverage. Improvements made in the formal verification toolset, including the introduction of semiformal verification and bounded-model-checking algorithms, have allowed increasingly larger partitions to become candidates for formal coverage. Other tool enhancements, such as phase-abstraction techniques to deal with clock gating schemes, are presented. Overall, numerous complex design defects were discovered using formal techniques across the microprocessor and communication subsystem, many of which would likely have escaped to the test floor.