VERIFY: a program for proving correctness of digital hardware designs
Artificial Intelligence - Special volume on qualitative reasoning about physical systems
Verification of Register Transfer Level Parallel Control Sequences
IEEE Transactions on Computers
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Complementary Definitions of Programming Language Semantics
Complementary Definitions of Programming Language Semantics
A formal design verification system based on an automated reasoning system
DAC '84 Proceedings of the 21st Design Automation Conference
Symbolic simulation for functional verification with ADLIB and SDL
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of hardware designs thru symbolic manipulation
Proceedings of the Symposium on Design Automation and Microprocessors
Symbolic simulation for correct machine design
DAC '79 Proceedings of the 16th Design Automation Conference
The application of program verification techniques to hardware verification
DAC '79 Proceedings of the 16th Design Automation Conference
ACM Transactions on Computer Systems (TOCS)
Formal verification of behavioral VHDL specifications: a case study
EURO-DAC '94 Proceedings of the conference on European design automation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
On diagnosis and correction of design errors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Practical Methodology for the Formal Verification of RISC Processors
Formal Methods in System Design
Proceedings of the conference on Design, automation and test in Europe
Design Methodology for a Large Communication Chip
IEEE Design & Test
Verification of Finite-State-Machine Refinements Using a Symbolic Methodology
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A symbolic core approach to the formal verification of integrated mixed-mode applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Verification of synthesized circuits at register transfer level with flow graphs
EURO-DAC '91 Proceedings of the conference on European design automation
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
A PN-based approach to the high-level synthesis of digital systems
Integration, the VLSI Journal
A PN-based approach to the high-level synthesis of digital systems
Integration, the VLSI Journal
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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Formal verification techniques are analyzed, focusing on two key points: suitable representation systems and mechanizable proofs. Different approaches to hardware verification are first examined, and formal verification and automated synthesis are compared to show how they cooperate in producing zero-defect designs. The different techniques are evaluated. Cross fertilization with software verification techniques is discussed.