An Introduction to Proving the Correctness of Programs
ACM Computing Surveys (CSUR)
PASCAL user manual and report
Developments in verification of design correctness (A Tutorial)
DAC '80 Proceedings of the 17th Design Automation Conference
Designing with LCD: language for computer design
DAC '77 Proceedings of the 14th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
Symbolic simulation for correct machine design
DAC '79 Proceedings of the 16th Design Automation Conference
Design verification based on functional abstraction
DAC '79 Proceedings of the 16th Design Automation Conference
Design and verification of large-scale computers by using DDL
DAC '79 Proceedings of the 16th Design Automation Conference
The application of program verification techniques to hardware verification
DAC '79 Proceedings of the 16th Design Automation Conference
A structural design language for computer aided design of digital systems
A structural design language for computer aided design of digital systems
Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A vertically integrated VLSI design environment
DAC '83 Proceedings of the 20th Design Automation Conference
Verification of synthesized circuits at register transfer level with flow graphs
EURO-DAC '91 Proceedings of the conference on European design automation
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The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence of different levels of abstraction and asynchronous timing. This paper motivates interest in this problem and provides background information on verification, ADLIB, and SDL. It then discusses approaches for dealing with the problems encountered in the symbolic simulation of ADLIB/SDL descriptions.