Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits

Authors:
N. Ishiura;M. Takahashi;S. Yajima
Affiliations:
Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN;Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN;Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Electronic Notes in Theoretical Computer Science (ENTCS)

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Abstract

As a new approach for timing verification of logic circuits, we propose a new concept of time-symbolic simulation. While a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. In this paper, we describe algorithms for time-symbolic simulation, and its application to hazard detection and verification of asynchronous sequential circuits.