Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic simulation for correct machine design
DAC '79 Proceedings of the 16th Design Automation Conference
NES: the behavioral model for the formal semantics of a hardware design language UDL/I
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Simulation of digital circuits in the presence of uncertainty
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Verification of asynchronous interface circuits with bounded wire delays
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Precise timing verification of logic circuits under combined delay model
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
EURO-DAC '91 Proceedings of the conference on European design automation
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. We are concerned with simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. We encode the cases of possible delay values of each gate by binary values and simulate all the possible combinations of the delay values by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.