Coded time-symbolic simulation using shared binary decision diagram
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Finite transition systems: semantics of communicating systems
Finite transition systems: semantics of communicating systems
Verification of Real-Time Systems using Linear Relation Analysis
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Automatic discovery of linear restraints among variables of a program
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Linear Parametric Model Checking of Timed Automata
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verification of Real-Time Systems by Successive Over and Under Approximation
Proceedings of the 7th International Conference on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Timed circuit verification using TEL structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of hazard-free asynchronous circuits with bounded wire delays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reasoning about synchronization in GALS systems
Formal Methods in System Design
The octahedron abstract domain
Science of Computer Programming
Time Separation of Events: An Inverse Method
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Timed verification of the generic architecture of a memory circuit using parametric timed automata
Formal Methods in System Design
Timing analysis of an embedded memory: SPSMALL
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Verification of the generic architecture of a memory circuit using parametric timed automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicablity of the approach.