Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders

Authors:
A. Neslin Ismailoglu;Murat Askar
Affiliations:
TUBITAK-UZAY, Department of Electrical and Electronics Engineering, Middle East Technical University, Balgat, Ankara, Turkey;TUBITAK-UZAY, Department of Electrical and Electronics Engineering, Middle East Technical University, Balgat, Ankara, Turkey
Venue:
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Year:
2008

Citing 14
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Abstract

Achievement of human-level machine intelligence has profound implications for modern society--a society which is becoming increasingly infocentric in its quest for efficiency, convenience and enhancement of quality of life. Humans have many remarkable ...