High-level design for asynchronous logic
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Speedup of NULL convention digital circuits using NULL cycle reduction
Journal of Systems Architecture: the EUROMICRO Journal
Asynchronous circuit design on reconfigurable devices
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Design of a logic element for implementing an asynchronous FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design and characterization of NULL convention arithmetic logic units
Microelectronic Engineering
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Automated energy calculation and estimation for delay-insensitive digital circuits
Microelectronics Journal
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT techniques and automation for asynchronous NULL conventional logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Journal of Electronic Testing: Theory and Applications
Advances in I/O, Speedup, and Universality on Colossus, an Unconventional Computer
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Asynchronous Solutions for Nanomagnetic Logic Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Designing robust threshold gates against soft errors
Microelectronics Journal
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
MTD3L: a secure IC design methodology with reduced overhead
ACMIN'12 Proceedings of the 14th international conference on Automatic Control, Modelling & Simulation, and Proceedings of the 11th international conference on Microelectronics, Nanoelectronics, Optoelectronics
Analog Integrated Circuits and Signal Processing
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NULL Convention Logic (NCL) is a symbolically complete logic which expresses process completely in terms of the logic itself and inherently and conveniently expresses asynchronous digital circuits. The traditional form of Boolean logic is not symbolically complete in the sense that it requires the participation of a fundamentally different form of expression, time in the form of the clock, which has to be very carefully coordinated with the logic part of the expression to completely and effectively express a process. We introduce NULL Convention Logic in relation to Boolean logic as a four value logic, and as a three value logic and finally as two value logic quite different from traditional Boolean logic. We then show how systems can be constructed entirely in terms of NULL Convention Logic.