An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
Estimation and bounding of energy consumption in burst-mode control circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
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ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
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Journal of Systems Architecture: the EUROMICRO Journal
Estimation of energy consumption in speed-independent control circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Design & Test
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Proceedings of the 20th symposium on Great lakes symposium on VLSI
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With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design's outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transistor-level simulation, and has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys. Both methods are applied to the NULL Convention Logic (NCL) DI paradigm, and are first demonstrated using a simple NCL sequencer, and then tested on a number of different NCL 4-bitx4-bit unsigned multiplier architectures. Energy per operation is automatically calculated for both methods, using an exhaustive testbench to simulate all input combinations and to check for functional correctness. The results show that both methods produce the desired output for all circuits, and that the gate-level switching approach developed herein produces results more than 1000 times as fast as transistor-level simulation, that fall within the range obtained by two different industry-standard transistor-level simulators. Hence, the developed energy estimation method is extremely useful for quickly determining how architecture changes affect energy usage.