Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Integration, the VLSI Journal
Self-timed rings and their application to division
Self-timed rings and their application to division
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
General Conditions for the Decomposition of State-Holding Elements
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
FLYSIG: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
Speedup of NULL convention digital circuits using NULL cycle reduction
Journal of Systems Architecture: the EUROMICRO Journal
Design of a logic element for implementing an asynchronous FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design and characterization of NULL convention arithmetic logic units
Microelectronic Engineering
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Automated energy calculation and estimation for delay-insensitive digital circuits
Microelectronics Journal
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Threshold gate with hysteresis using neuron MOS
ISTASC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 7
DFT techniques and automation for asynchronous NULL conventional logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Journal of Electronic Testing: Theory and Applications
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Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of four or fewer variables, thus facilitating a variety of gate-level optimizations. TCR optimizations are formalized for NCL and then assessed by comparing levels of gate delays, gate counts, transistor counts, and power utilization of the resulting designs. The methods are illustrated to produce (1) fundamental logic functions that are 2.2-2.3 times faster and require 40-45% fewer transistors than conventional canonical designs, (2) a Full Adder with reduced critical path delay and transistor count over various alternative gate-level synthesis approaches, resulting in a circuit with at least 48% fewer transistors, half as many gate delays to generate the carry output, and the same number of gate delays to generate the sum output, as its nearest competitors, and (3) time, space, and power optimized increment circuits for a 4-bit up-counter, resulting in a throughput-optimized design that is 14% and 82% faster than area- and power-optimized designs, respectively, an area-optimized design that requires 22% and 42% fewer transistors than the speed- and power-optimized designs, respectively, and a power-optimized design that dissipates 63% and 42% less power than the speed- and area-optimized designs, respectively. Results demonstrate support for a variety of optimizations utilizing conventional Boolean minimization followed by table-driven gate substitutions, providing for an NCL design method that is readily automatable.