Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
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In this article threshold gates with hysteresis using neuron MOS (νMOS) are presented as basic elements in Null Convention Logic (NCL) circuits. NCL, which proposed by K. M. Fant and S. A. Branst, needs special gates having hysteresis, because NCL uses different ternary logic systems in computation phase and wiping phase of asynchronous behavior, respectively. To impliment the dinamic behavior, The traditional NCL circuits exploit extended CMOS structure which consists of a number of cascaded and parallel transistors connections. Then we improve the circuti with the characteristics of threshold function in νMOS, we designed hysteresial νMOS by means of feedback loop. This results the asynchronous circuits reducing the number of MOS and wire area. We provide two synthesis methods and simulation results of the gates and full-adder. The evaluation results of area dissipation and average delay show the advantages of the proposed circuitry.