The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Integration, the VLSI Journal
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
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EURO-DAC '94 Proceedings of the conference on European design automation
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Single-rail handshake circuits
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Threshold gate with hysteresis using neuron MOS
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Handshake circuits can be mapped onto QDI circuits using generic standard-cells only. Despite several interesting optimizations, the resulting circuits are large. By extending the isochronic-fork assumption, we arrive at a class of asynchronous circuits that particularly allow efficient realizations of double-rail data paths. This paper defines the extended isochronic fork, discusses its implementation, and provides numerous examples. The impact on circuit costs is evaluated for a DCC error decoder. In an appendix a basic arbiter (mutual-exclusion element) is presented that requires simple CMOS gates only. We also propose a 3-way generalization of this arbiter.