The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Exact two-level minimization of hazard-free logic with multiple-input changes
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Integration, the VLSI Journal
Synthesis and verification of asynchronous circuits from graphical specifications
Synthesis and verification of asynchronous circuits from graphical specifications
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Design of Asynchronous Circuits Assuming Unbounded Gate Delays
IEEE Transactions on Computers
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Different types of hazards have been studied extensively under the bounded gate and wire delay model. It is well known that under this delay model not all multiple input dynamic logic hazards can be removed from all two stage combinational logic circuits. In this paper we restrict the delay model to the well-known inertial gate delay or speed independent model and show that under this model half of the dynamic logic hazards can no longer occur in two level logic circuits. We then weaken the zero wire delay restriction and find an upper bound for the delay along critical interconnection wires and hence propose a virtual isochronic fork model for interconnection networks. Index terms- Asynchronous circuits, combinational logic, delay models, hazards, isochronic forks, signal transition graphs (STGs), speed independent circuits (SICs).